Integrated circuits (ICs) have become an integral part of nearly all electronic devices today. Advantages to using ICs generally include low power consumption and low profiles that have made devices significantly more portable than previous generations of devices. ICs may include a combination of logic circuitry and memory devices that make up familiar devices such as microprocessors and random access memory. The microprocessors in personal computers (PCs) are general purpose devices that can perform a number of diverse tasks. However, many electronic devices perform very specific functions and do not need a general purpose microprocessor.
Application-specific integrated circuits (ASICs) are integrated circuits designed to perform specific tasks. ASICs may be found in a wide range of devices including, for example, cellular telephones, automobiles, or alarm clocks. ASICs are made up of cells that perform smaller tasks that when connected together accomplish the desired function of the ASIC. The cells include register cells for processing data and memory cells for storing data. Because all of the cells cooperate with each other the cells must be synchronized. Synchronization is accomplished by distributing a clock signal to all of the cells.
The clock signal repeats a cycle including a voltage rise, referred to as a rising edge, followed by a voltage drop, referred to as a falling edge. The rising and falling edges are detected by the cells and used to time events throughout all of the cells in an ASIC. These events include, for example, some cells placing information on a data bus and other cells latching onto information on a data bus. If the clock signal does not arrive at all of the cells at substantially similar times, the cells will fail to operate as desired. For example, if the clock signal arrives at a first cell latching onto a data bus before the clock signal arrives at a second cell placing data on the data bus, the first cell will not obtain correct data because it will try to obtain data that has not been placed on the data bus. As a result the cell and possibly the entire ASIC will not function properly. The time for the clock signal to propagate from a root, or insertion point for the clock signal, to each cell is referred to as an insertion delay.
The clock signal is distributed over a clock tree to the cells. In this sense, the clock tree is the backbone of ASIC design. One problem with the clock signal is that the clock signal does not arrive at all cells at identical times because the length of wire or interconnect between different cells and the clock root are not identical. The propagation time of the clock signal through the wire or interconnect is finite and therefore the clock signal takes different amounts of time to reach each cell depending on the length of the wire or interconnect leading to each cell.
An additional problem lies in skew of the clock signal. As the clock signal propagates through the clock tree, the rising edges and falling edges become less sharp resulting in a larger skew of the clock signal. A low skew is important for the cells to detect the rising and falling edges of the clock signal. Over an extended distance, the clock signal can experience large skew and appear to be a continuously variable signal rather than a signal with two discrete values. As a result, the cells do not function at proper times within an ASIC.
Synthesis tools are developed to assist ASIC designers to ensure the clock signal reaches each cell of an ASIC at substantially identical times. The designer begins by laying out cells for an ASIC. The synthesis tool then lays out a clock tree design that reduces skew to an acceptable level as input by the designer. The synthesis tool also optimizes the clock tree design to ensure that each cell in an ASIC receives the clock signal at substantially identical times within an acceptable limit as input by the designer.
One technique previous synthesis tools have used is to strategically place buffers along the clock tree to act as delays. The buffers are also placed to reduce skew in the clock signal by reducing the load on each buffer. The load on each buffer is determined by the length of wire or interconnect between buffers because the capacitance of the wire or interconnect is proportional to its length. Additional buffers are placed along the clock tree to delay the propagation of the clock signal. However, this technique is unable to meet the clock skew and clock timing requirements of new ASIC designs.
Another technique uses an H-tree to place buffers along the clock tree in a symmetric fashion. When the buffers are arranged symmetrically the length of wire or interconnect between cells in the ASIC is substantially identical. As a result, the cells experience similar insertion delays and clock skew. Current clock tree synthesis tools are capable of designing H-trees. However, they lack the capability of specifying the length of the interconnect between the insertion point and the cells.
In ASIC designs, the H-trees achieve good clock skew. Without knowledge of how a tool creates an H-tree design, however, current tools might not give satisfactory H-tree design results. If the H-tree synthesis could be customized, the user would have more flexibility to create a satisfactory H-tree design.
Therefore, a new technique for generating clock trees in ASICs is needed that produces low skew and similar insertion delay for each of the cells and allows design flexibility.